Name | Last modified | Size | Description | |
---|---|---|---|---|
Parent Directory | - | |||
_index.md | 2023-09-14 00:01 | 1.3K | ||
build-verible.sh | 2023-09-14 00:01 | 2.0K | ||
build_consts.sh | 2023-09-14 00:01 | 2.6K | ||
build_docs.py | 2023-09-14 00:01 | 9.4K | ||
container/ | 2023-09-14 00:01 | - | ||
dashboard/ | 2023-09-14 00:01 | - | ||
diff_generated_util_output.py | 2023-09-14 00:01 | 5.9K | ||
dvsim.py | 2023-09-14 00:01 | 15K | ||
dvsim/ | 2023-09-14 00:01 | - | ||
embedded_target.py | 2023-09-14 00:01 | 2.5K | ||
example/ | 2023-09-14 00:01 | - | ||
export_target.sh | 2023-09-14 00:01 | 771 | ||
fix_include_guard.py | 2023-09-14 00:01 | 2.8K | ||
fpga/ | 2023-09-14 00:01 | - | ||
fpvgen.py | 2023-09-14 00:01 | 4.6K | ||
fpvgen/ | 2023-09-14 00:01 | - | ||
get-toolchain.py | 2023-09-14 00:01 | 5.0K | ||
i2csvg.py | 2023-09-14 00:01 | 5.0K | ||
i2csvg/ | 2023-09-14 00:01 | - | ||
lint_commits.py | 2023-09-14 00:01 | 5.2K | ||
lintpy.py | 2023-09-14 00:01 | 5.4K | ||
make_distribution.sh | 2023-09-14 00:01 | 1.7K | ||
openocd/ | 2023-09-14 00:01 | - | ||
reggen/ | 2023-09-14 00:01 | - | ||
regtool.py | 2023-09-14 00:01 | 7.6K | ||
rom_chip_info.py | 2023-09-14 00:01 | 2.1K | ||
run-clang-format.sh | 2023-09-14 00:01 | 1.0K | ||
simplespi/ | 2023-09-14 00:01 | - | ||
syn_yosys.sh | 2023-09-14 00:01 | 2.6K | ||
test_reggen/ | 2023-09-14 00:01 | - | ||
testplanner.py | 2023-09-14 00:01 | 1.1K | ||
testplanner/ | 2023-09-14 00:01 | - | ||
tlgen.py | 2023-09-14 00:01 | 2.9K | ||
tlgen/ | 2023-09-14 00:01 | - | ||
topgen.py | 2023-09-14 00:01 | 21K | ||
topgen/ | 2023-09-14 00:01 | - | ||
uvmdvgen.py | 2023-09-14 00:01 | 4.4K | ||
uvmdvgen/ | 2023-09-14 00:01 | - | ||
vendor.py | 2023-09-14 00:01 | 17K | ||
verible-format.sh | 2023-09-14 00:01 | 1.0K | ||
verible-style-lint.sh | 2023-09-14 00:01 | 733 | ||
wavegen/ | 2023-09-14 00:01 | - | ||
wavetool.py | 2023-09-14 00:01 | 3.6K | ||